This application relates generally to processing systems, and, more particularly, to filtering requests to a translation lookaside buffer in a processing system.
Processing devices such as central processing units (CPUs), graphics processing units (GPUs), or accelerated processing units (APUs) typically implement virtual memory systems. Processes in an operating system that uses virtual memory are configured to access memory using virtual addresses. For example, a store instruction can write information from a register to a memory location indicated by a virtual address or a load instruction can load a register with information read from a memory location indicated by a virtual address. Processing systems that implement virtual memory use a page table to store the mapping between the virtual addresses and physical addresses in memory. However, accessing the page table to acquire the physical address corresponding to a virtual address is a relatively time-consuming activity that may introduce significant latency into the system.
Conventional processing devices may therefore implement a translation lookaside buffer (TLB) that can cache mappings of virtual addresses to physical addresses in locations that are physically or logically closer to processing elements such as a load-store unit. For example, a TLB can cache virtual-to-physical address mappings of recently requested addresses. The TLB is typically implemented as content-addressable memory (CAM) that uses the virtual address as a search key and the search result is a physical address indicated by the stored mapping. If the requested address is present in the TLB, a TLB hit, the search yields a match and the retrieved physical address can be used to access memory. If the requested address is not in the TLB, a TLB miss, the translation proceeds by looking up the page table in a process called a tablewalk. The tablewalk is an expensive process that involves reading the contents of multiple memory locations and using them to compute the physical address. After the physical address is determined by the tablewalk, the virtual address to physical address mapping is entered into the TLB.